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general description the MAX8660/max8661 power management ics (pmics) power intel xscale applications processors in smart cellular phones, pdas, internet appliances, and other portable devices. four step-down dc-dc outputs, three linear regulators, and an 8th always-on ldo are integrated with power- management functions. two dynamically controlled dc- dc outputs power the processor core and internal mem- ory. two other dc-dc converters power i/o, memory, and other peripherals. additional functions include on/off control for outputs, low-battery detection, reset output, and a 2-wire i 2 c ? serial interface. the max8661 functions the same as the MAX8660, except it lacks the reg1 step-down regulator and the reg7 linear regulator. all step-down dc-to-dc outputs use fast 2mhz pwm switching and tiny external components. they automati- cally switch from pwm to high-efficiency light-load operation to reduce operating current and extend bat- tery life. in addition, a forced pwm option allows low- noise operation at all loads. overvoltage lockout pro- tects the device against inputs up to 7.5v. applications pdas, palmtops, and wireless handhelds smart cell phones personal media players portable gps navigation digital cameras features optimized for intel xscale processors protected to 7.5vshutdown above 6.3v four synchronous step-down converters reg1, reg2, reg3, reg4 four ldo regulators reg5, reg6, reg7, reg8 2mhz switching allows small components low, 20 a deep-sleep current low-battery monitor and reset output MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications ________________________________________________________________ maxim integrated products 1 ordering information 19-0587; rev 0; 8/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part pin- package pkg code options MAX8660 etl+ 40 thin qfn 5mm x 5mm t4055-1 v 1: 3.3v , 3.0v , 2.85v v 2: 3.3v , 2.5v , 1.8v m ax 8660ae tl+ * 40 thin qfn 5mm x 5mm t4055-1 v 1: 2.5v , 2.0v , 1.8v v 2: 2.5v , 2.0v , 1.8v max8661 etl+ 40 thin qfn 5mm x 5mm t4055-1 n o re g1 and re g7 v 2: 3.3v , 2.5v , 1.8v note: all devices are specified over the -40? to 85? operating temperature range. + denotes lead-free package. * future product?ontact factory for availability. MAX8660aetl+ MAX8660etl+ max8661etl+ thin qfn 5mm x 5mm x 0.8mm ( ) are for the max8661 top view 35 36 34 33 12 11 13 v5 lx4 pg4 set2 v6 14 in5 lx3 en5 ramp pv3 rso v3 mr lbr 1 2 pg1 (gnd) 4567 27 28 29 30 26 24 23 22 lx1 (n.c.) pv1 (pv) in in8 pg2 lx2 pv4 pg3 3 25 37 en1 (gnd) pv2 38 39 40 v1 (gnd) set1 (gnd) v4 lbo sda scl srad 32 15 agnd en2 31 16 17 18 19 20 v8 in67 (in6) v7 (n.c.) v2 lbf 8910 21 en34 exposed pad (ep) pin configuration v1 v2 v3 v4 v5 v6 v7 vcc_io: (pin prog) 3.3v/3.0v/2.85v at 1.2a vcc_mem: (pin prog) 1.8v/2.5v/3.3v at 0.9a vcc_apps: (i 2 c prog) 0.725 to 1.8v, dvm at 1.6a vcc_sram: (i 2 c prog) 0.725 to 1.8v, dvm at 0.4a vcc_mvt: (i 2 c prog) 1.7v to 2.0v at 200ma vcc_card1: (i 2 c prog) 1.8v to 3.3v at 500ma vcc_card2: (i 2 c prog) 1.8v to 3.3v at 500ma mr rso lbr lbo en1,2,5 en34 nreset nbatt_fault sys_en pwr_en main battery in v8 vcc_bbatt: 3.3v always on at 30ma lbf i 2 c interface scl sda MAX8660 simplified functional diagram ? purchase of i 2 c components from maxim integrated products, inc., or one of its sublicensed associated companies, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. intel xscale is a registered trademark of intel corp.
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications 2 _______________________________________________________________________________________ table of contents general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 simplified functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 maxim vs. intel terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 step-down dc-dc converters (reg1?eg4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 reg1 (vcc_io) step-down dc-dc converter (MAX8660 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 reg2 (vcc_io, vcc_mem) step-down dc-dc converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 reg3 (vcc_apps) step-down dc-dc converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 7 reg4 (vcc_sram) step-down dc-dc converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 7 reg1?eg4 step-down dc-dc converter operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 reg1?eg4 synchronous rectification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 reg1/reg2 100% duty-cycle operation (dropout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 linear regulators (reg5?eg8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 reg5 (vcc_mvt, vcc_bg, vcc_osc13m, vcc_pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 reg6/reg7 (vcc_card1, vcc_card2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 reg8 (vcc_bbatt) always-on regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ramp rate control (ramp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 enable signals (en_, pwr_en, sys_en, i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 reg3/reg4 enable (en34, en3, en4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 power-up and power-down timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 intel xscale power configuration register (pcfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 voltage monitors, reset, and undervoltage-lockout functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 undervoltage and overvoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 reset output ( rso ) and mr input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 low-battery detector, ( lbo , lbf, lbr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 internal off-discharge resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 thermal-overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 slave address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 i 2 c write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications _______________________________________________________________________________________ 3 table of contents (continued) design procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 setting the output voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 pc board layout and routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 chip information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 tables table 1. maxim and intel power domain terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 2. maxim and intel digital signal terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 3. set1 logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 4. set2 logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 5. enable signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 6. truth table for v3/v4 enable logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 7. power modes and corresponding quiescent operating currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 8. internal off-discharge resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 9. i 2 c registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 10. dvm voltage change register (vcc1, 0x20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 11. serial codes for v3 (vcc_apps) and v4 (vcc_sram) output voltages. . . . . . . . . . . . . . . . . . . . . . 36 table 12. serial codes for v5 output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 13. serial codes for v6 and v7 output voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figures figure 1. example MAX8660 connection to intel xscale processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 2. functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 3. typical applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 4. soft-start and voltage-change ramp rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 5. v3/v4 enable logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 6. power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 7. low-battery detector functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 8. start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 9. acknowledge bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 10. slave address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 11. writing to the MAX8660/max8661 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications 4 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in = v in5 = v in67 = v in8 = 3.6v, figure 3, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: lx_ has internal clamp diodes to pg_ and pv_. applications that forward bias these diodes must take care not to exceed the ic? package power-dissipation limits. in, in5, in6, in67, en2, en34, en5, lbo , rso , mr , set1, set2, v1, v2, v3, v4, scl, sda, srad to agnd..................................................-0.3v to +7.5v lbf, lbr, en1, ramp to agnd .................-0.3v to (v in + 0.3v) v8 to agnd................................................-0.3v to (v in8 + 0.3v) v5 to agnd................................................-0.3v to (v in5 + 0.3v) v6, v7 to agnd........................................-0.3v to (v in67 + 0.3v) pv1 to pg1 ............................................................-0.3v to +7.5v pv2 to pg2 ............................................................-0.3v to +7.5v pv3 to pg3 ............................................................-0.3v to +7.5v pv4 to pg4 ............................................................-0.3v to +7.5v pv, pv1, pv2, pv3, pv4, in8 to in ........................-0.3v to +0.3v lx1 continuous rms current (note 1) .................................2.3a lx2 continuous rms current (note 1) .................................2.0a lx3 continuous rms current (note 1) .................................2.6a lx4 continuous rms current (note 1) .................................1.0a pg1, pg2, pg3, pg4, ep to agnd.......................-0.6v to +0.6v gnd to agnd ......................................................-0.3v to +0.3v all regx output short-circuit duration......................continuous continuous power dissipation (t a = +70?) 40-pin thin qfn (derate 35.7mw/? above +70?).....2857mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units pv1, pv2, pv3, pv4, in, in8 supply voltage range v in pv1, pv2, pv3, pv4, in, and in8 must be connected together externally 2.6 6.0 v v in rising 2.250 2.400 2.550 in undervoltage-lockout threshold v uvlo v in falling 2.200 2.350 2.525 v v in rising 6.20 6.35 6.50 in overvoltage-lockout threshold v ovlo v in falling 6.00 6.15 6.30 v only v8 on (deep-sleep power mode) 20 v1, v2, and v8 on; v1 and v2 in normal (skip) operating mode 50 v1, v2, v5, and v8 on (sleep power mode); v1 and v2 in normal (skip) operating mode 90 v 1, v 2, v 3, v 4, v 5, and v 8 on ( r un p ow er m od e) ; v 1, v 2, v 3, and v 4 i n nor m al ( ski p ) op er ati ng m od e 140 no load; sda = scl = v8 v 1, v 2, v 3, v 4, v 5, v 6, v 7, and v 8 ( al l on) ; v 1, v 2, v 3, and v 4 i n nor m al ( ski p ) op er ati ng m od e 250 undervoltage lockout, v in = 2.2v 1.5 input current i in + i pv1 +i pv2 + i pv3 +i pv4 + i in5 + i in67 + i in8 overvoltage lockout, v in = 6.5v 25 ?
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications _______________________________________________________________________________________ 5 electrical characteristics (continued) (v in = v in5 = v in67 = v in8 = 3.6v, figure 3, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units pwm switching frequency f sw 1.9 2.0 2.1 mhz reg1?ynchronous step-down dc-dc converter (MAX8660, MAX8660a only) set1 = in, v pv1 = 4.2v, load = 600ma 3.250 3.300 3.350 set1 not connected = v pv1 = 3.6v, load = 600ma 2.955 3.000 3.045 v1 voltage accuracy?ax8860 v1 set1 = agnd, v pv1 = 3.6v, load = 600ma 2.807 2.850 2.893 v set1 = in, v pv1 = 4.2v, load = 600ma 2.463 2.500 2.538 set1 not connected, v pv1 = 3.6v, 600ma 1.970 2.000 2.030 v1 voltage accuracy?ax8660a v1 set1 = agnd, 3.6v, load = 600ma 1.773 1.800 1.827 v v1 load regulation load = 0 to 1200ma -1.5 %/a v1 line regulation 0.15 %/v set1 input leakage current 0.01 ? load = 800ma (notes 3, 4) 150 v1 dropout voltage load = 1200ma (notes 3, 4) 200 mv p-channel on-resistance 0.12 ? n-channel on-resistance 0.15 ? p-channel current-limit threshold 1.5 1.8 2.2 a n-channel zero-crossing threshold 25 ma n-channel negative current limit forced-pwm mode only -975 ma reg1 maximum output current i out1 2.6v v pv1 6v (note 5) 1.2 a v1 bias current 5a t a = +25 c-2 0.03 +2 lx1 leakage current v pv1 = 6v, lx1 = pg1 or pv1, v en1 = 0v t a = +85 c 0.2 ? soft-start ramp rate?ax8660 to v1 = 3.3v (total ramp time is 450? for all v1 output voltages) 5 7 9 mv/? soft-start ramp rate MAX8660a to v1 = 2.5v (total ramp time is 450? for all v1 output voltages) 3 5 7 mv/? v5 to v1 enable time t vmhvsh1 figure 6 350 ? internal off-discharge resistance 650 ? minimum duty cycle forced-pwm mode only, min duty cycle in skip mode is 0% 16.7 % maximum duty cycle 100 %
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications 6 _______________________________________________________________________________________ electrical characteristics (continued) (v in = v in5 = v in67 = v in8 = 3.6v, figure 3, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units reg2?ynchronous step-down dc-dc converter set2 = in, v pv2 = 4.2v, load = 600ma 3.250 3.300 3.350 set2 not connected, v pv2 = 3.6v, load = 600ma 2.463 2.500 2.538 v2 voltage accuracy?ax8660 v2 set2 = agnd, v pv2 = 3.6v, load = 600ma 1.773 1.800 1.827 v set2 = in, v pv2 = 4.2v, load = 600ma 2.463 2.500 2.538 set2 not connected, v pv2 = 3.6v, load = 600ma 1.970 2.000 2.030 v2 voltage accuracy?ax8660a v2 set2 = agnd, v pv2 = 3.6v, load = 600ma 1.773 1.800 1.827 v v2 load regulation load = 0 to 900ma -1.7 %/a v2 line regulation 0.15 %/v set2 input leakage current 0.01 ? v2 dropout voltage load = 900ma (notes 3, 4) 225 mv p-channel on-resistance 0.18 ? n-channel on-resistance 0.15 ? p-channel current-limit threshold 1.10 1.30 1.50 a n- c hannel z er o c r ossi ng thr eshol d 25 ma n-channel negative current limit forced-pwm mode only -800 ma reg2 maximum output current i out2 2.6v v pv2 6v (note 5) 0.9 a v2 bias current 5a t a = +25? -2 ?.03 +2 lx2 leakage current v pv2 = 6v, lx2 = pg2 or pv2, v en2 = 0v t a = +85? 0.2 ? soft-start ramp rate to v2 = 1.8v (total ramp time is 450? for all v2 output voltages) 2 4 6 mv/? v5 to v2 enable time t vmhvsh2 figure 6 350 ? internal off-discharge resistance 650 ? minimum duty cycle forced-pwm mode only; min duty cycle in skip mode is 0% 16.7 % maximum duty cycle 100 % reg3?ynchronous step-down dc-dc converter reg3 default output voltage, v pv3 = 3.6v, load = 600ma 1.379 1.400 1.421 v v3 output voltage accuracy v3 reg3 serial programmed from 0.9v to 1.8v, load = 600ma (note 6) -1.5 +1.5 % v3 load regulation load = 0 to 1600ma -17 mv/a v3 line regulation (note 7) 0.05 %/v p-channel on-resistance 0.12 ? n-channel on-resistance 0.08 ?
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications _______________________________________________________________________________________ 7 electrical characteristics (continued) (v in = v in5 = v in67 = v in8 = 3.6v, figure 3, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units p-channel current-limit threshold 1.85 2.15 2.45 a n- c hannel z er o- c r ossi ng thr eshol d 25 ma n-channel negative current limit forced-pwm mode only -0.8 a reg3 maximum output current i out3 2.6v v pv3_ 6v (note 5) 1.6 a v3 bias current 0.01 ? t a = +25 c -2 +0.03 +2 lx3 leakage current v pv3 = 6v, lx3 = pg3 or pv3, v en34 = 0v t a = +85 c 0.24 ? soft-start ramp rate r ramp = 56k ? to 1.4v 8 mv/? v3 dynamic-change ramp rate r ramp = 56k ? 10 mv/? en34 to v3 enable time t phlvth3 p ow er i ng up to 1.4v , fi g ur e 6, r ram p = 56k ? 400 ? internal off-discharge resistance 550 ? minimum duty cycle forced-pwm mode only, min duty cycle in skip mode is 0% 16.7 % maximum duty cycle 100 % reg4?ynchronous step-down dc-dc converter reg4 default output voltage, v pv3 = 3.6v, load = 200ma 1.379 1.400 1.421 v v4 output voltage accuracy v4 reg4 serial programmed from 0.9v to 1.8v, load = 200ma (note 6) -1.5 +1.5 % v4 load regulation load = 0 to 400ma -40 mv/a v4 line regulation (note 7) 0.1 %/v p-channel on-resistance 0.37 ? n-channel on-resistance 0.3 ? p-channel current-limit threshold 0.05 0.78 0.90 a n- c hannel z er o- c r ossi ng thr eshol d 25 ma n-channel negative current limit forced-pwm mode only -975 ma reg4 maximum output current i out4 2.6v v pv3 6v (note 5) 0.4 a v4 bias current 0.01 ? t a = +25 c-2 0.02 +2 lx4 leakage current v pv4 = 6v, lx4 = pg4 or pv4, v en34 = 0v t a = +85 c 0.12 ? soft-start ramp rate r ramp = 56k ? to 1.4v 8 mv/? v4 dynamic-change ramp rate r ramp = 56k ? 10 mv/? en34 to v4 enable time t phlvth4 p ow er i ng up to 1.4v , fi g ur e 6, r ram p = 56k ? 400 ? internal off-discharge resistance 550 ? minimum duty cycle forced-pwm mode only, min duty cycle in skip mode is 0% 16.7 % maximum duty cycle 100 %
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications 8 _______________________________________________________________________________________ electrical characteristics (continued) (v in = v in5 = v in67 = v in8 = 3.6v, figure 3, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units reg5 ldo in5 input voltage range v in5 2.35 v in v reg5 default output voltage, 2.35v v in5 6v, load = 0 to 200ma 1.764 1.800 1.836 v v5 output voltage v5 reg5 serial programmed from 1.7v to 2.0, 2.35v v in5 6v, load = 0 to 200ma -2 +2 % v5 output current limit i out5 225 350 500 ma v5 output-voltage noise 10hz to 100khz, i out5 = 10ma 160 ? rms v5 power-supply rejection v in5 = (v5 + 1v), i out5 = 10ma, f = 10khz 40 db v5 soft-start ramp rate powering up to 1.8v (total ramp time is 225? for all v5 output voltages) 5 7 9 mv/? en5 to v5 enable time t sehvmh figure 6 290 ? v5 dynamic-change ramp rate r ramp = 56k ? 10 mv/? internal off-discharge resistance 2k ? reg6, reg7 ldos in67 input voltage range v in67 2.35 v in v reg6 and reg7 output voltage (por default to 0v, set by serial input) v6 v7 setting from 1.8v to 3.3v in 0.1v steps, load = 0 to 300ma -3 +3 % v6, v7 dropout voltage 3v mode, load = 300ma (note 3) 55 100 mv v6, v7 output current limit i out6 i out7 v in67 = 3.6v 750 ma v6, v7 soft-start ramp rate powering up to 3.3v, (total ramp time is 450? for all v6/v7 output voltages) 5 7 9 mv/? internal off-discharge resistance 350 ? reg8 always-on ldo load = 0 to 15ma 3.168 3.300 3.432 v8 output voltage v8 load = 30ma 2.800 3.2 3.432 v v8 dropout voltage load = 15ma (note 3) 180 mv v8 output current limit i out8 v8 = 2.5v 30 70 135 ma internal off-discharge resistance 1.5 k ? low-battery detector (lbf, lbr, lbo ) low-battery falling threshold v lbfth 1.182 1.200 1.218 v low-battery rising threshold v lbrth 1.231 1.250 1.268 v lbo , rso output-high leakage current v in = 6v, t a = +25 c 0.2 ? 2.6v v in 6v, sinking 3ma 0.2 lbo output low level v in = 1v, sinking 100? 0.4 v minimum v in for lbo assertion lbo is forced low when the device is in uvlo 1v
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications _______________________________________________________________________________________ 9 electrical characteristics (continued) (v in = v in5 = v in67 = v in8 = 3.6v, figure 3, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units lbo deassert delay t vbhbfh figure 6 0 3 s t a = +25 c -50 0 +50 lbf and lbr input bias current t a = +85 c 0.5 na reset ( mr , rso) rso threshold v rsoth voltage on v8, falling, hysteresis is 5% (typ) 2.1 2.2 2.3 v rso deassert delay t vbhrsth figure 6 20 24 28 ms rso output-high leakage current v in = 6v, t a = +25 c 0.2 ? 2.6v v in 6v, sinking 3ma 0.2 rso output low level v in = 1v, sinking 100? 0.4 v minimum v in for rso assertion rso is forced low when the device is in uvlo 1v mr input high level 2.6v v in 6v 1.4 v mr input low level 2.6v v in 6v 0.4 v mr input leakage current v in = 6v, t a = +25 c -0.2 +0.2 a mr minimum pulse width t mr 1s thermal-overload protection thermal-shutdown temperature t j rising +160 c thermal-shutdown hysteresis 15 c enable inputs (en1, en2, en34, en5) en_ input high level 2.6v v in 6v 1.4 v en_ input low level 2.6v v in 6v 0.4 v en_ input leakage current v in = 6v, t a = +25 c -0.2 +0.2 a i 2 c logic (sda, scl, srad) scl, sda input high voltage 1.4 v scl, sda input low voltage 0.4 v scl, sda input hysteresis 0.1 v scl, sda input current t a = +25 c, in = agnd, v in = 6v -10 +10 ? sda output low voltage 2.6v v in 6v, sinking 3ma 0.2 v srad input high level 2.6v v in 6v 1.4 v srad input low level 2.6v v in 6v 0.4 v srad input leakage current v in = 6v, t a = +25 o c -0.2 +0.2 a
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications 10 ______________________________________________________________________________________ parameter symbol conditions min typ max units i 2 c timing clock frequency f scl 400 khz hold time (repeated) start condition t hd ; sta figure 8 0.6 ? clk low period t low 1.3 ? clk high period t high 0.6 ? set-up time for a repeated start condition t su;sta figure 8 0.6 ? data hold time t hd ; dat figure 9 0 ? data set-up time t su ; dat figure 9 100 ns set-up time for stop condition t su ; sto figure 8 0.6 ? bus-free time between stop and start t buf 1.3 ? maximum pulse width of spikes that must be suppressed by the input filter of both data and clk signals 50 ns electrical characteristics (continued) (v in = v in5 = v in67 = v in8 = 3.6v, figure 3, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 2) note 2: limits are 100% production tested at t a = +25?. limits over the operating temperature range are guaranteed through cor- relation using statistical quality control (sqc) methods. note 3: the dropout voltage is defined as v in - v out when v out is 100mv below the nominal value of v out . note 4: dropout voltage (v do ) is a function of the p-channel switch resistance (r pch ) and the inductor resistance (r l ). the given values assume r l = 50m ? for the reg1 inductor and 67m ? for the reg2 inductor: v do = i load (r p + r l ) note 5: the maximum output current (i out(max) ) is: where: r n = n-channel synchronous rectifier rds (on) r p = p-channel power switch rds (on) r l = external inductor esr i out(max) = maximum output current provided by the pmic i out(target) = maximum desired output current f = operating frequency minimum l = external inductor value note 6: tested at 1.4v, default output voltage. note 7: all output voltages are possible in normal mode. in forced-pwm mode, the minimum output voltage is limited by 0.167 x v in . for example, with v in = 5.688v, the minimum output is 0.95v. i i vd xfxl rr d xfxl out max lim out nl () () () () = ? ? ++ ? 1 2 1 1 2
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications ______________________________________________________________________________________ 11 quiescent current vs. input voltage input voltage (v) input current ( a) MAX8660/61 toc01 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 10 20 30 40 50 60 70 80 90 100 sda = sdl = v8 reg1?eg7 disabled reg8 is always on switching frequency vs. input voltage input voltage (v) switching frequency (mhz) MAX8660 toc02 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 switching frequency vs. temperature temperature ( c) switching frequency (mhz) MAX8660 toc03 -40 -15 10 35 60 85 1.7 1.8 1.9 2.0 2.1 2.2 2.3 en1/en2/en5 enable response MAX8660 toc04 5v/div en1/en2/en5 v2 v5 v1 1v/div 1v/div 1v/div 100 s/div en34 enable response MAX8660 toc05 2v/div en34 v3 v4 500mv/div 500mv/div 100 s/div r ramp = 56k ? typical operating characteristics (circuit of figure 3, v in = 3.6v, t a = +25?, unless otherwise noted.)
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications 12 ______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 3, v in = 3.6v, t a = +25?, unless otherwise noted.) reg1 output voltage vs. temperature temperature ( c) output voltage (v) MAX8660 toc10 -40 -15 10 35 60 85 3.20 3.22 3.24 3.26 3.28 3.30 3.32 3.34 3.36 3.38 3.40 600ma load reg1 dropout voltage vs. load current load current (ma) dropout voltage (mv) MAX8660 toc11 0 200 400 600 800 1000 1200 0 50 100 150 200 250 300 the nominal esr of toko's 1.2 h de2812c inductor is 44m ? . the nominal p-channel resistance of the reg1 is 120m ? . the slope of this line shows that the total reg1 dropout resistance of an average part, board, inductor combination is 172m ? . reg1 load transient MAX8660 toc12 100mv/div v1 i v1 500mv/div 40 s/div v1 = 3.3v 3.8v input 10ma 800ma reg 1 heavy-load switching waveforms MAX8660 toc13 2v/div 2mv/div v lx1 v1 i l1 1a/div 0a 400ns/div 4.2v input 1a load reg1 light-load switching waveforms MAX8660 toc14 2v/div 20mv/div v lx1 v1 i l1 200ma/div 0a 2 s/div 3.8v input, 20ma load 100 95 90 85 80 75 70 65 60 55 50 0.01 1 0.1 10 100 1000 10,000 reg1 efficiency vs. load current MAX8660 toc06 load current (ma) efficiency (%) v1 = 3.3v l1 = 1.2 h (toko de2812c) v in = 4.2v v in = 3.6v forced-pwm normal reg1 output voltage vs. input voltage input voltage (v) output voltage (v) MAX8660 toc07 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 i load = 1000ma i load = 10ma 3.3v output dropout reg1 line transient MAX8660 toc08 1v/div v in v1 100mv/div 40 s/div 600ma load, v1 = 3.3v 5.0v 3.6v reg1 load regulation load current (ma) output voltage (v) MAX8660 toc09 0 200 400 600 800 1000 1200 3.20 3.22 3.24 3.26 3.28 3.30 3.32 3.34 3.36 3.38 3.40 v in = 3.8v -1.5%/a forced-pwm normal
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications ______________________________________________________________________________________ 13 reg2 output voltage vs. input voltage input voltage (v) output voltage (v) MAX8660 toc16 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.65 1.70 1.75 1.80 1.85 1.90 1.95 10ma load 800ma load reg2 line transient MAX8660 toc17 1v/div 100mv/div v in v2 40 s/div 450ma load, v2 = 1.8v 5.0v 3.6v typical operating characteristics (continued) (circuit of figure 3, v in = 3.6v, t a = +25?, unless otherwise noted.) reg2 load regulation load current (ma) output voltage (v) MAX8660 toc18 0 200 400 600 800 1.75 1.77 1.79 1.81 1.83 1.85 v in = 3.6v -1.7%/a forced-pwm normal reg2 output voltage vs. temperature temperature ( c) output voltage (v) MAX8660 toc19 -40 -15 10 35 60 85 1.70 1.72 1.74 1.76 1.78 1.80 1.82 1.84 1.86 1.88 1.90 800ma load reg2 dropout voltage vs. load current load current (ma) dropout voltage (mv) MAX8660 toc20 0 200 400 600 800 1000 0 50 100 150 200 250 300 the nominal esr of toko's 2.0 h de2812c inductor is 67m ? . the nominal p-channel resistance of the reg2 is 180m ? . the slope of this line shows that the total reg2 dropout resistance of an average part, board, inductor combination is 255m ? . reg2 load transient MAX8660 toc21 200ma/div 100mv/div v2 i v2 20 s/div v2 = 1.8v 10ma 600ma reg2 efficiency vs. load current load current (ma) efficiency (%) MAX8660 toc15 50 55 60 65 70 75 80 85 90 95 0.01 0.1 1 10 100 1000 v in = 4.2v v in = 3.6v l2 = 2.0 h (toko de2812c) v2 = 1.8v forced-pwm normal reg2 heavy-load switching waveforms MAX8660 toc22 2mv/div 0a 2v/div 1a/div v2 i l2 v lx2 400ns/div 800ma load reg2 light-load switching waveforms MAX8660 toc23 20mv/div 0a 2v/div 200ma/div v2 i l2 v lx2 2 s/div 30ma load
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications 14 ______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 3, v in = 3.6v, t a = +25?, unless otherwise noted.) reg3 output voltage vs. temperature temperature ( c) output voltage (v) MAX8660 toc28 -40 -15 10 35 60 85 1.30 1.32 1.34 1.36 1.38 1.40 1.42 1.44 1.46 1.48 1.50 i load = 1000ma reg3 voltage change response MAX8660 toc29 500mv/div 500mv/div v3 rising v3 falling 100 s/div active ramp-down enabled r ramp = 56k ? r ramp = 248k ? r ramp = 248k ? r ramp = 56k ? 1.8v 1.8v 0.725v 0.725v reg3 load transient MAX8660 toc30 50mv/div 500mv/div v3 i v3 20 s/div 10ma 900ma reg3 heavy-load switching waveforms MAX8660 toc31 2v/div 2mv/div 1a/div 0a v lx3 v3 i l3 400ns/div 1500ma load reg3 light-load switching waveforms MAX8660 toc32 2v/div 20mv/div 200ma/div 0a v lx3 v3 i l3 2 s/div 30ma load reg3 efficiency vs. load current load current (ma) efficiency (%) MAX8660 toc24 50 55 60 65 70 75 80 85 90 0.01 0.1 1 10 100 1000 10,000 l3 = 1.2 h (toko de2812c) v3 = 1.4v v in = 4.2v v in = 3.6v forced-pwm normal reg3 output voltage vs. input voltage input voltage (v) output voltage (v) MAX8660 toc25 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.35 1.36 1.37 1.38 1.39 1.40 1.41 1.42 1.43 1.44 1.45 i load = 1000ma reg3 line transient MAX8660 toc26 50mv/div 1v/div v in v3 40 s/div 800ma load, v3 = 1.4v 5.0v 3.6v reg3 load regulation load current (ma) output voltage (v) MAX8660 toc27 0 200 400 600 800 1000 1200 1400 1600 1.36 1.37 1.38 1.39 1.40 1.41 1.42 1.43 1.44 v in = 3.6v forced-pwm normal
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications ______________________________________________________________________________________ 15 reg4 efficiency vs. load current load current (ma) efficiency (%) MAX8660 toc33 50 55 60 65 70 75 80 85 90 95 0.01 0.1 1 10 100 1000 l4 = 4.7 h (toko de2812c) v4 = 1.4v v in = 4.2v v in = 3.6v forced-pwm normal typical operating characteristics (continued) (circuit of figure 3, v in = 3.6v, t a = +25?, unless otherwise noted.) reg4 output voltage vs. input voltage input voltage (v) output voltage (v) MAX8660 toc34 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.35 1.36 1.37 1.38 1.39 1.40 1.41 1.42 i load = 300ma reg4 line transient MAX8660 toc35 1v/div 10mv/div v in v4 40 s/div 200ma load, v5 = 1.4v 5.0v 3.6v reg4 heavy-load switching waveforms MAX8660 toc40 2v/div 2mv/div 200ma/div 0a v lx4 v4 i l4 400ns/div 200ma load reg4 light-load switching waveforms MAX8660 toc41 2v/div 20mv/div 200ma/div 0a v lx4 v4 i l4 2 s/div 18ma load reg4 load regulation load current (ma) output voltage (v) MAX8660 toc36 0 100 200 300 400 1.36 1.37 1.38 1.39 1.40 1.41 1.42 1.43 1.44 v in = 3.6v forced-pwm normal reg4 output voltage vs. temperature temperature ( c) output voltage (v) MAX8660 toc37 -40 -15 10 35 60 85 1.20 1.25 1.30 1.35 1.40 1.45 1.50 400ma load reg4 voltage change response MAX8660 toc38 500mv/div 500mv/div v4 rising v4 falling 100 s/div active ramp-down enabled r ramp = 56k ? r ramp = 248k ? r ramp = 248k ? r ramp = 56k ? 0.725v 0.725v 1.8v 1.8v reg4 load transient response MAX8660 toc39 50mv/div 200mv/div v4 i v4 20 s/div 10ma 350ma
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications 16 ______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 3, v in = 3.6v, t a = +25?, unless otherwise noted.) reg5 output voltage vs. input voltage input voltage (v) output voltage (v) MAX8660 toc42 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.77 1.78 1.79 1.80 1.81 1.82 1.83 100ma load reg5 output voltage vs. load current load current (ma) output voltage (v) MAX8660 toc43 0 50 100 150 200 1.77 1.78 1.79 1.80 1.81 1.82 1.83 reg5 output voltage vs. temperature temperature ( c) output voltage (v) MAX8660 toc44 -40 -15 10 35 60 85 1.77 1.78 1.79 1.80 1.81 1.82 1.83 100ma load reg5 line transient MAX8660 toc45 1v/div 20mv/div v in v5 40 s/div 100ma load, v5 = 1.8v 3.6v 5.0v 100ma load reg5 load transient response MAX8660 toc46 100ma/div 50mv/div v5 i v5 20 s/div 100ma load, v5 = 1.8v 180ma 10ma reg5 voltage change response MAX8660 toc47 100mv/div v5 40 s/div r ramp = 56k ? 2.0v 1.725v reg5 output noise spectral density vs. frequency frequency (khz) noise density (nv/ (hz)) MAX8660 toc48 0.01 0.1 1 10 100 10 100 1000 10,000 reg5 output noise (0.1hz to 10hz) MAX8660 toc49 10 v/div 1s/div reg5 psrr vs. frequency frequency (khz) psrr (db) MAX8660 toc50 0 10 20 30 40 50 60 70 80 0.01 0.1 1 10 100 r load = 180 ?
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications ______________________________________________________________________________________ 17 typical operating characteristics (continued) (circuit of figure 3, v in = 3.6v, t a = +25?, unless otherwise noted.) reg6/reg7 output voltage vs. input voltage input voltage (v) output voltage (v) MAX8660 toc51 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.77 1.78 1.79 1.80 1.81 1.82 1.83 100ma load reg6/reg7 output voltage vs. load current load current (ma) output voltage (v) MAX8660 toc52 0 100 200 300 400 500 600 700 800 900 1.0 1.5 2.0 2.5 3.0 3.5 4.2v input 3.3v output 2.4v input 1.8v output reg6/reg7 output voltage vs. temperature temperature ( c) output voltage (v) MAX8660 toc53 -40 -15 10 35 60 85 1.70 1.72 1.74 1.76 1.78 1.80 1.82 1.84 1.86 1.88 1.90 300ma load reg6/reg7 line transient MAX8660 toc54 1v/div v6/v7 v in 40 s/div 300ma load, v6/v7 = 1.8v 20mv/div 3.6v 5.0v reg6/reg7 load transient MAX8660 toc55 100ma/div i v6 /i v7 v6/v7 10 s/div v6/v7 = 1.8v 50mv/div 10ma 300ma reg6/reg7 enable waveform MAX8660 toc56 500mv/div 2v/div v sda v6/v7 100 s/div i 2 c enable signal 60 s reg6/reg7 dropout output voltage vs. load current load current (ma) dropout voltage (mv) MAX8660 toc57 0 100 200 300 400 500 0 20 40 60 80 100 120 140 3.3v output 3.0v output the slope of these lines shows that the reg6/reg7 dropout resistance of an average part mounted on the maxim evaluation kit is 205m ? .
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications 18 ______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 3, v in = 3.6v, t a = +25?, unless otherwise noted.) reg8 output voltage vs. input voltage input voltage (v) output voltage (v) MAX8660 toc58 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 5ma load reg8 load regulation load current (ma) v8 (v) MAX8660 toc59 0 1020304050607080 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 v in = 3.6v reg8 output voltage vs. temperature temperature ( c) output voltage (v) MAX8660 toc60 -40 -15 10 35 60 85 3.20 3.22 3.24 3.26 3.28 3.30 3.32 3.34 3.36 3.38 3.40 5ma load reg8 line transient MAX8660 toc61 50mv/div 1v/div v in v8 40 s/div 10ma load 3.6v 5.0v reg8 load transient MAX8660 toc62 50mv/div 10ma/div v8 i v8 10 s/div 5ma 15ma reg8 dropout voltage vs. load current load current (ma) dropout voltage (mv) MAX8660 toc63 0 5 10 15 20 25 30 0 50 100 150 200 250 300 350 400 the slope of this line shows that the reg8 dropout resistance of an average part mounted on the maxim evaluation kit is 12.4 ? .
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications ______________________________________________________________________________________ 19 pin description name pin MAX8660 max8661 function 1 in5 in5 reg5 power input. connect in5 to in to ensure v5 rises first to meet intel sequencing requirements. if adherence to intel specifications is not required, in5 can be connected to v1, v2, or another supply between 2.35v and v in . see the linear regulators (reg5?eg8) section for more information . 2 v5 v5 reg5 linear-regulator output. v5 defaults to 1.8v and is adjustable from 1.7v to 2.0v through the serial interface. the input to the v5 regulator is in5. use v5 to power vcc_mvt, vcc_bg, vcc_osc13m, and vcc_pll on intel xscale processors. v5 is internally pulled to agnd through 2k ? when reg5 is shut down. 3 pv4 pv4 reg4 power input. connect a 4.7? ceramic capacitor from pv4 to pg4. all pv pins and in must be connected together externally. 4 lx4 lx4 re g 4 s w i tchi ng n od e. c onnect lx 4 to the re g4 i nd uctor . lx 4 i s hi g h i m p ed ance w hen re g4 i s shut d ow n. 5 pg4 pg4 re g 4 p ow er g r ound . c onnect p g 1, p g 2, p g 3, p g 4, and ag n d tog ether . refer to the m ax 8660 e v ki t data sheet for more information. 6 set2 set2 reg2 voltage select input. set2 is a tri-level logic input. connect set2 to select the v2 output voltage as detailed in table 4. the reg2 output voltage selected by set2 is latched at the end of the reg2 soft-start period. changes to set2 after the startup period have no effect. 7 v6 v6 reg6 linear-regulator output. reg6 is activated and programmed through the serial interface to output from 1.8v to 3.3v in 0.1v steps. reg6 is off by default. v6 is internally pulled to agnd through 350 ? when reg6 is shut down. v6 optionally powers vcc_card1 on intel xscale processors. in67 reg6 and reg7 power input. in67 is typically connected to in. in67 can also be connected to any supply between 2.35v to v in . 8 in6 reg6 power input. in6 is typically connected to in. in6 can also be connected to any supply between 2.35v to v in . v7 reg7 linear-regulator output. reg7 is activated and programmed through the serial interface to output from 1.8v to 3.3v in 0.1v steps. reg7 is off by default. v7 is internally pulled to agnd through 350 ? when reg7 is shut down. v7 optionally powers vcc_card2 on intel xscale processors. 9 n.c. no internal connection 10 v2 v2 reg2 voltage sense input. connect v2 directly to the reg2 output voltage. the output voltage of reg2 is selected by set2. v2 is internally pulled to agnd through 650 ? when reg2 is shut down. v2 powers vcc_mem on intel xscale processors. 11 scl scl serial-clock input. see the i 2 c interface section. 12 sda sda serial-data input. see the i 2 c interface section. 13 lbo lbo low-battery output. lbo is an open-drain output that pulls low when lbf is below its threshold. lbo typically connects to the nbatt_fault input of the intel xscale processor to indicate that the battery has been removed or discharged. 14 pv2 pv2 reg2 power input. connect a 4.7? ceramic capacitor from pv2 to pg2. all pv pins and in must be connected together externally. 15 lx2 lx2 re g 2 s w i tchi ng n od e. c onnect lx 2 to the re g2 i nd uctor . lx 2 i s hi g h i m p ed ance w hen re g2 i s shut d ow n. 16 pg2 pg2 re g 2 p ow er g r ound . c onnect p g 1, p g 2, p g 3, p g 4, and ag n d tog ether . refer to the m ax 8660 e v ki t data sheet for more information. 17 in8 in8 reg8 input power connection. in8 must be connected to in. 18 in in main battery input. this input provides power to the ic. connect a 0.47? ceramic capacitor from in to agnd.
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications 20 ______________________________________________________________________________________ pin description (continued) name pin MAX8660 max8661 function 19 agnd agnd analog ground. connect pg1, pg2, pg3, pg4, and agnd together. refer to the MAX8660 ev kit data sheet for more information. 20 v8 v8 reg8 always-on 3.3v ldo output. reg8 is the first regulator that powers up in the MAX8660/max8661. reg8 is supplied from in and supplies up to 30ma. v8 is internally pulled to agnd through 1.5k ? during in undervoltage or overvoltage lockout. connect v8 to vcc_bbatt on intel xscale processors. 21 lbf lbf low-battery detect falling input. the lbf threshold is 1.20v. connect lbf to lbr for 50mv hysteresis. use a three-resistor voltage-divider for larger hysteresis. lbf sets the falling voltage at which lbo goes low. see the low-battery detector ( lbo , lbf, lbr) section for more information. 22 lbr lbr low-battery detect rising input. the lbr threshold is 1.25v. connect lbf to lbr for 50mv hysteresis. use a three-resistor voltage-divider for larger hysteresis. lbr sets the rising voltage at which lbo goes high. see the low-battery detector ( lbo , lbf, lbr) section for more information. 23 mr mr manual reset input. a low mr input causes rso to go low and resets all serial programmed registers to their default values. see the reset output ( rso ) and mr input section for more information. 24 ramp ramp ramp-rate input. connect a resistor from ramp to agnd to set the regulator ramp rates. see the ramp-rate control (ramp) section for more information. 25 en5 en5 reg5 enable input. drive en5 high to turn on reg5. en5 has hysteresis so an rc can be used to implement manual sequencing with respect to other inputs. en5 is typically driven by the sys_en output of an intel xscale processor. 26 pg3 pg3 re g 3 p ow er g r ound . c onnect p g 1, p g 2, p g 3, p g 4, and ag n d tog ether . refer to the m ax 8660 e v ki t data sheet for more information. 27 lx3 lx3 re g 3 s w i tchi ng n od e. c onnect lx 3 to the re g3 i nd uctor . lx 3 i s hi g h i m p ed ance w hen re g3 i s shut d ow n. 28 pv3 pv3 reg3 power input. connect a 4.7 f ceramic capacitor from pv3 to pg3. all pv pins and in must be connected together externally. 29 rso rso open-drain reset output. rso typically connects to the nreset input on an intel xscale processor. an output low from the MAX8660/max8661 rso resets all serial programmed registers to their default values and causes the processor to enter its reset state. see the reset output ( rso ) and mr input section for more information. 30 v3 v3 reg3 voltage sense input. connect v3 directly to the reg3 output voltage. the output voltage d efaul ts to 1.4v and i s ad j ustab l e fr om 0.725v to 1.8v thr oug h the ser i al i nter face. v 3 i s i nter nal l y p ul l ed to agn d thr oug h 550 ? w hen re g3 i s shut d ow n. v 3 connects to v c c _ap p s on intel x s cal e p r ocessor s. 31 en34 en34 reg3 and reg4 active-high hardware enable input. drive en34 high to enable both reg3 and reg4. drive en34 low to allow the serial interface to enable reg3 and reg4 independently. en34 has hysteresis so an rc can be used to implement manual sequencing with respect to other inputs. en34 is typically driven by the pwr_en output of an intel xscale processor. see the reg3/reg4 enable (en34, en3, en4) section for more information. 32 en2 en2 reg2 enable input. drive en2 high to turn on reg2. en2 has hysteresis so that an rc can be used to implement manual sequencing with respect to other inputs. en2 is typically driven by the sys_en output of an intel xscale processor. 33 srad srad serial-address input. connect srad to agnd for a 7-bit slave address of 0110 100 (0x68). connect srad to in to change the address to 0110 101 (0x6a). the eighth slave address bit is always zero since the MAX8660/max8661 are write-only. see the slave address section for more information. pg1 re g 1 p ow er g r ound . c onnect p g 1, p g 2, p g 3, p g 4, and ag n d tog ether . refer to the m ax 8660 e v ki t data sheet for more information. 34 gnd ground. connect all gnd pins to ep.
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications ______________________________________________________________________________________ 21 detailed description the MAX8660/max8661 pmics are optimized for devices using the next-generation intel xscale proces- sors, including smart cellular phones, pdas, internet appliances, and other portable devices requiring sub- stantial computing and multimedia capability and low power consumption. the MAX8660/max8661 comply with intel xscale processor specifications. as shown in figure 2, the MAX8660 integrates eight high-performance, low-operating-current power sup- plies. reg1?eg4 are step-down dc-dc converters, and reg5?eg8 are linear regulators. other functions include low-battery detection ( lbo ), a reset output ( rso ), a manual reset input ( mr ), and a 2-wire i 2 c seri- al interface. the max8661 functions the same as the MAX8660, but does not have the reg1 step-down reg- ulator and the reg7 linear regulator. the operating input voltage range is from 2.6v to 6.0v, allowing use with a 1-cell li+ battery, 3-cell nimh, or a 5v input. input protection is provided with undervoltage and overvoltage lockouts. overvoltage lockout protects the device against inputs up to 7.5v. maxim vs. intel terminology the MAX8660/max8661 are compatible with intel? next-generation xscale processor. figure 1 shows one of many possible connections between the intel xscale processor and the MAX8660/max8661. to facilitate system development with intel processors, this docu- ment uses both maxim and intel terminology. intel ter- minology appears in parentheses and italics. for example, this document refers to ?8 ( vcc_bbatt) because the MAX8660 v8 output powers the intel vcc_bbatt power domain. tables 1 and 2 outline maxim and intel terminology. name pin MAX8660 max8661 function lx1 reg1 switching node. connect lx1 to the reg1 inductor. lx1 is high impedance when reg1 is shutdown. 35 n.c. no internal connection pv1 reg1 power input. connect a 4.7? ceramic capacitor from pv1 to pg1. all pv pins and in must be connected together externally. 36 pv power input. all pv pins and in must be connected together externally. en1 reg1 enable input. drive en1 high to turn on reg1. en1 has hysteresis so that an rc can be used to implement manual sequencing with respect to other inputs. en1 is typically driven by the sys_en output of an intel xscale processor. 37 gnd ground. connect all gnd pins to ep. v1 reg1 voltage sense input. connect v1 directly to the reg1 output voltage. the output voltage of reg1 is selected by set1. connect v1 to vcc_iox for intel xscale processors. v1 is internally pulled to agnd through 650 ? when reg1 is shut down. 38 gnd ground. connect all gnd pins to ep. set1 reg1 voltage select input. set1 is a tri-level logic input. connect set1 to select the v1 output voltage as detailed in table 3. the reg1 output voltage selected by set1 is latched at the end of the reg1 soft-start period. changes to set1 after the startup period have no effect. 39 gnd ground. connect all gnd pins to ep. 40 v4 v4 reg4 feedback sense input. connect v4 directly to the reg4 output voltage. the reg4 output voltage defaults to 1.4v and is adjustable from 0.725v to 1.8v with the serial interface. v4 is internally pulled to agnd through 550 ? when reg4 is shut down. v4 powers vcc_sram on intel xscale processors. ep ep ep exposed pad. connect the exposed pad to ground. connecting the exposed pad to ground does not remove the requirement for proper ground connections to pg1, pg2, pg3, pg4, and agnd. the exposed pad is attached with epoxy to the substrate of the die, making it an excellent path to remove heat from the ic. pin description (continued)
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications 22 ______________________________________________________________________________________ auxiliary power auxiliary power sd/cf memory card 1 sd/cf memory card 2 sys_en pwr_en nreset nbatt_fault sda {gpio33} scl {gpio32} pwr_sda pwr_scl lbo in v1 i 2 c rso en1 en2 en5 en34 vcc_i01 vcc_i03 vcc_i04 vcc_i06 vcc_lcd vcc_msl vcc_df vcc_ci vcc_mem vcc_apps vcc_sram vcc_mvt vcc_bg vcc_pll vcc_osc13m vcc_card1 vcc_card2 vcc_bbatt vcc_usb vcc_tsi intel xscale processor v8 (vcc_bbatt) MAX8660 auxiliary power peripherals auxilary power peripherals memory 3.3v at 1200ma 1.8v at 900ma 3.3v at 30ma 0.725v to 1.8v (def 1.4v) at 1600ma 0.725v to 1.8v (def 1.4v) at 400ma 1.7v to 2.0v (def 1.8v) at 200ma 1.8v to 3.3v (def 0v) at 500ma 1.8v to 3.3v (def 0v) at 500ma v2 v3 v4 v5 v6 v7 v8 1045ma 135ma 160ma 540ma 40ma 485ma 485ma 25ma standard i 2 c power i 2 c 15ma 10ma 25ma 50ma 50ma 55ma 20ma 50ma 35ma 200ma 1600ma 360ma 15ma 15ma 5ma 5ma figure 1. example MAX8660 connection to intel xscale processor. this is one example only. other connections are also supported.
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications ______________________________________________________________________________________ 23 MAX8660 max8661 in en1 en2 in8 to in v8 v6 in67 (in6) v7 scl sda srad vcc_iox rso from cpu sys_en ( ) are for the max8661 ramp lbr (1.25v) lbo lbf (1.20v) batt v1 set1 pv1 pwm on step-down pwm reg1 pg1 lx1 to batt v1, vcc_i0x, vcc_lcd, vcc_msl, vdd_usb, vcc_df, vdd_ci, vcc_tsi MAX8660; 3.3v, 3.0v, 2.85v MAX8660a; 2.5v, 2.0v, 1.8v 1200ma (MAX8660/MAX8660a only) latch v2 set2 pv2 pwm on step-down pwm reg2 pg2 lx2 to batt v2, vcc_mem MAX8660/max8661; 3.3v, 2.5v, 1.8v MAX8660a; 2.5v, 2.0v, 1.8v 900ma latch v3 en34 pv3 pwm ramp on step-down pwm reg3 pg3 lx3 to batt from cpu pwr_en v3, vcc_apps 0.725v to 1.8v (default 1.4v) 1.6a adj 0.725v to 1.8v v4 in5 v5 en5 pv4 pwm ramp step-down pwm reg4 pg4 lx4 to batt to in, v1 or v2 v4, vcc_sram 0.725v to 1.8v (default 1.4v) 400ma ramp adj 1.7v to 2.0v adj 0.725v to 1.8v open-drain low batt out to nbatt_fault battery agnd uvlo ovlo and batt mon ref 1.25v to all blocks v8, vcc_bbatt (3.3v 30ma, always on) v6, vcc_card1 0v/1.8?.3v (default 0v) 500ma v7, vcc_card2 0v/1.8?.3v (default 0v) 500ma (MAX8660/MAX8660a only) reset v8 < 2.4v 20ms set rate ramp mr hardware reset input to cpu nreset ldo reg 8 ldo reg 7 ldo reg 6 to v1, v2, or in v5, vcc_mvt, vcc_bg, 1.7v to 2.0v (default 1.8v) 200ma ldo reg 5 from cpu sys_en ep agnd pgnd i 2 c serial interface logical or (figure 5) figure 2. functional diagram
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications 24 ______________________________________________________________________________________ figure 3. typical applications circuit u1 MAX8660 MAX8660a v8 v1 in 35 34 lx1 pg1 38 v1 36 pv1 c2 10 f c1 10 f c11 4.7 f c22 0.47 f l1 1.2 h v2 in 15 16 lx2 pg2 10 v2 14 pv2 c6 10 f c7 10 f c15 4.7 f l2 2.0 h v3 in 27 26 lx3 pg3 30 v3 28 pv3 c4 10 f c5 10 f c3 10 f c12 4.7 f l3 1.2 h v4 in 4 5 lx4 pg4 40 v4 3 pv4 c9 10 f c8 10 f c18 4.7 f l4 4.7 h v5 in 2 v5 1 in5 c13 2.2 f v7 9 v7 c16 4.7 f v6 7 v6 c17 4.7 f c19 1 f c10 0.1 f r6 300k ? c21 0.1 f in 8 11 in67 scl agnd pgnd scl c20 1 f ep note: reference designators match MAX8660evkit 12 sda sda 20 v8 6 set2 set2 39 set1 set1 25 en5 en5 31 32 37 en34 en34 en2 en2 en1 en1 18 in 21 lbf 22 lbr 19 agnd 13 lbo lbo 24 ramp r4 56k ? 33 srad 17 in8 29 rso rso 23 mr mr r5 300k ? v8 v8 in in r3 1m ? r2 80.6k ? r1 1.82m ? r10 20 ? 2.6v to 6.0v input r7 300k ? v8 s1
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications ______________________________________________________________________________________ 25 step-down dc-dc converters (reg1?eg4) reg1 (vcc_io) step-down dc-dc converter (MAX8660 only) reg1 is a high-efficiency (reg1 + reg8 i q = 40?) 2mhz current-mode step-down converter that outputs up to 1200ma with efficiency up to 96% (see the typical operating characteristics ). the output voltage (v1) is selected with the set1 input as shown in table 3. the reg1 output voltage selection is latched at the end of the reg1 soft-start period. changes in set1 after the startup period have no effect. en1 is a dedicated enable input for reg1. drive en1 high to enable reg1 or drive en1 low to disable reg1. intel power domain intel power domain acceptable voltage compatible maxim power domain description vcc_io1 vcc_io3 vcc_io4 vcc_io6 1.8v ?0% or 3.0v ?0% or 3.3v ?0% v1 or v2 ? peripheral i/o supply for uarts, standard i 2 c, power i 2 c, audio interface, ssps, pwms, etc. ( vcc_io1,vcc_io3, vcc_io4, vcc_io6 ) vcc_lcd vcc_msl vcc_ci vcc_df 1.8v ?0% or 3.0v ?0% v1 or v2 ? lcd interface logic ( vcc_lcd ) ? fast serial interface ( vcc_msl ) ? camera flash interface ( vcc_ci ) ? data flash interface ( vcc_df ) vcc_mem 1.8v ?00mv v2 ? i/o supply for high-speed memory vcc_apps 0.95v to 1.41v ?% v3 ? main processor core vcc_sram 1.08v to 1.41v ?00mv v4 ? internal sram memory vcc_mvt vcc_bg vcc_osc13m vcc_pll 1.8v ?00mv v5 ? internal logic and i/o blocks ( vcc_mvt ) ? bandgap reference ( vcc_bg ) ? 13mhz oscillator (vcc_osc13m) ? phase-locked loop (pll) and oscillator ( vcc_pll ) vcc_card1 1.8v ?0% or 3.0v ?0% or 3.3v ?0% v6 ? removable storage and usim card supply vcc_card2 1.8v ?0% or 3.0v ?0% or 3.3v ?0% v7 ? removable storage and usim card supply vcc_bbatt 3.0v ?v v8 ? regulated battery voltage vcc_usb 3.3v ?00mv v1 or v2 (if programmed to 3.3v) ? universal serial bus ( vcc_usb ) vcc_tsi 3.3v ?00mv v1 or v2 (if programmed to 3.3v) ? touch-screen interface ( vcc_tsi ) table 1. maxim and intel power domain terminology
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications 26 ______________________________________________________________________________________ en1 has hysteresis so that an rc may be used to imple- ment manual sequencing with respect to other inputs. in systems based on intel xscale processors, en1, en2, and en5 are typically connected to sys_en (table 2). the reg1 step-down regulator operates in either nor- mal or forced-pwm mode. see the reg1?eg4 step- down dc-dc converter operating modes section for more information. reg1 has an on-chip synchronous rectifier. see the reg1?eg4 synchronous rectification section for more information. the reg1 regulator allows 100% duty-cycle operation. see the reg1/reg2 100% duty-cycle operation (dropout) section for more information. reg2 (vcc_io, vcc_mem) step-down dc-dc converters reg2 is a high-efficiency (reg2 + reg8 i q = 40?) 2mhz current-mode step-down dc-dc converter that outputs up to 900ma with efficiency up to 96%. the output voltage is selected with the set2 input as shown in table 4. the reg2 output voltage selection is latched at the end of the reg2 soft-start period. changes in set2 after the startup period have no effect. en2 is a dedicated enable input for reg2. drive en2 high to enable reg2 or drive en2 low to disable reg2. en2 has hysteresis so that an rc may be used to implement manual sequencing with respect to other inputs. in systems based on intel processors, en1, en2, and en5 are typically connected to sys_en (table 2). the reg2 step-down regulator operates in either nor- mal or forced-pwm mode. see the reg1?eg4 step- down dc-dc converter operating modes section for more information. the reg2 regulator has an on-chip synchronous rectifier. see the reg1?eg4 synchronous rectification section for more information. maxim intel description en34 pwr_en active-high enable signal for processor core power. the intel xscale processor drives this pwr_en signal high to exit sleep mode. the processor? pwr_en logic is powered by the MAX8660/max8661 ?lways on?v8 ( vcc_bbatt ) regulator during sleep mode. en1, en2, en5 sys_en active-high enable signal for peripheral power supplies. the intel xscale processor drives this sys_en signal high to enter run mode. rso nreset active-low reset. the MAX8660/max8661 drive this signal low to reset the processor. when rso goes low, the MAX8660/max8661 i 2 c registers are reset to their default values. lbo nbatt_fault active-low battery fault. the MAX8660/max8661 drive this signal low to signal the processor that the battery has been removed or discharged. sda gpio33 pwr_sda i 2 c serial-data input/output. the MAX8660/max8861 sda generally connects to both the xscale processor? standard i 2 c data line ( gpio33 ) and its dedicated power i 2 c data line. this connection operates as an i 2 c multimaster system with the MAX8660/max8661 accepting commands from both the standard i 2 c and the power i 2 c. scl gpio32 pwr_scl i 2 c serial clock. the MAX8660/max8661 scl generally connects to both the xscale processor? standard i 2 c clock line ( gpio32 ) and its dedicated power i 2 c clock line. this connection operates as an i 2 c multimaster system with the MAX8660/max8661 accepting commands from both the standard i 2 c and the power i 2 c. table 2. maxim and intel digital signal terminology set1* MAX8660: v1 (v) MAX8660a: v1 (v) in 3.3 2.5 unconnected 3.0 2.0 ground 2.85 1.8 table 3. set1 logic set2* MAX8660, max8661: v2 (v) MAX8660a: v2 (v) in 3.3 2.5 unconnected 2.5 2.0 ground 1.8 1.8 table 4. set2 logic *set1 is latched after reg1 startup. *set2 is latched after reg2 startup.
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications ______________________________________________________________________________________ 27 the reg2 regulator allows 100% duty-cycle operation. see the reg1/reg2 100% duty-cycle operation (dropout) section for more information. reg3 (vcc_apps) step-down dc-dc converters reg3 is a high-efficiency (reg3 + reg8 i q = 45?) 2mhz current-mode step-down converter that has an i 2 c-adjustable output voltage from 0.725v to 1.800v in 25mv increments with efficiency up to 92%. the default reg3 output voltage is 1.4v (contact factory for other default voltages). reg3 delivers up to 1.6a. see the i 2 c interface section for details on how to adjust the output voltage. reg3 has an i 2 c enable bit (en3) and a shared hard- ware enable pin (en34). see the reg3/reg4 enable (en34, en3, en4) section for more information. the reg3 step-down regulator operates in either nor- mal or forced-pwm mode. see the reg1?eg4 step- down dc-dc converter operating modes section for more information. the reg3 regulator has an on-chip synchronous rectifier. see the reg1?eg4 synchronous rectification section for more information. reg4 (vcc_sram) step-down dc-dc converters reg4 is a high-efficiency (reg4 + reg8 i q = 45?) 2mhz current-mode step-down converter that has an i 2 c-adjustable output voltage from 0.725v to 1.800v in 25mv increments with efficiency up to 92%. the default reg4 output voltage is 1.4v (contact factory for other default voltages). reg4 delivers up to 400ma. see the i 2 c interface section for details on how to adjust the output voltage. reg4 has an i 2 c enable bit (en4) and a shared hard- ware enable pin (en34). see the reg3/reg4 enable (en34, en3, en4) section for more information. the reg4 step-down regulator operates in either nor- mal or forced-pwm mode. see the reg1?eg4 step- down dc-dc converter operating modes section for more information. the reg4 regulator has an on-chip synchronous rectifier. see the reg1?eg4 synchronous rectification section for more information. reg1?eg4 step-down dc-dc converter operating modes reg1?eg4 independently operate in one of two modes: normal or forced pwm. at power-up or after a reset, reg1?eg4 default to normal operation. activate forced-pwm mode by setting bits in the fpwm register (table 9) with the i 2 c interface. the fpwm bits can be changed at any time. in forced-pwm mode, a converter operates with a con- stant 2mhz switching frequency regardless of output load. the MAX8660/max8661 regulate the output volt- age by modulating the switching duty cycle. forced- pwm mode is ideal for low-noise systems because output voltage ripple is small (< 10mv pp ) and switching harmonics occur at multiples of the constant-switching frequency and are easily filtered. however, light-load power consumption in forced-pwm mode is higher than that of normal mode (table 7). normal operation offers improved efficiency at light loads by switching only as necessary to supply the load. with moderate to heavy loading, the regulator switches at a fixed 2mhz switching frequency as it does in forced-pwm mode. this transition to fixed-fre- quency switching occurs at the load current specified in the following equation: reg1?eg4 synchronous rectification internal n-channel synchronous rectifiers eliminate the need for external schottky diodes and improve efficien- cy. the synchronous rectifier turns on during the second half of each switching cycle (off-time). during this time, the voltage across the inductor is reversed, and the inductor current ramps down. in pwm mode, the syn- chronous rectifier turns off at the end of the switching cycle. in normal mode, the synchronous rectifier turns off when the inductor current falls below 25ma or at the end of the switching cycle, whichever occurs first. reg1/reg2 100% duty-cycle operation (dropout) the reg1 and reg2 step-down dc-dc converters operate with 100% duty cycle when the supply voltage approaches the output voltage. this allows these con- verters to maintain regulation until the input voltage falls below the desired output voltage plus the dropout volt- age specification of the converter. during 100% duty- cycle operation, the high-side p-channel mosfet turns on constantly, connecting the input to the output through the inductor. the dropout voltage (v do ) is cal- culated as follows: v do = i load (r p + r l ) where: r p = p-channel power switch r ds(on) r l = external inductor esr the reg1 dropout voltage is 200mv with a 1200ma load (with inductor resistance = 50m ? ). the reg2 dropout voltage is 225mv with a 900ma load (with inductor resistance = 67m ? ). i vv xl x v vxf out in out out in sw ? ? 2
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications 28 ______________________________________________________________________________________ linear regulators (reg5?eg8) reg5 (vcc_mvt, vcc_bg, vcc_osc13m, vcc_pll) reg5 is a linear regulator with an i 2 c-adjustable output voltage from 1.700v to 2.000v in 25mv increments (reg5 + reg8 i q = 55?). the default reg5 voltage is 1.8v. reg5 delivers up to 200ma. see the i 2 c interface section for details on how to adjust the output voltage. the power input for the reg5 linear regulator is in5. the in5 input voltage range extends down to 2.35v. note that in the intel xscale specification, vcc_mvt is enabled by sys_en (along with v1 and v2), but must not rise after v1 ( vcc_i/o ) or v2 ( vcc_mem ). this requirement dictates that in5 be connected to in and not v1 or v2. en5 is a dedicated enable input for reg5. drive en5 high to enable reg5. drive en5 low to disable reg5. en5 has hysteresis so that an rc may be used to imple- ment manual sequencing with respect to other inputs. in systems with intel xscale processors, en1, en2, and en5 are typically connected to sys_en (table 2). reg6/reg7 (vcc_card1, vcc_card2) the reg6/reg7 linear regulators supply up to 500ma each (reg6 or reg 7 + reg8 i q = 85?). the output voltages, v6 and v7, are programmable through the serial interface from 1.8v to 3.3v in 0.1v steps (table 13). see the i 2 c interface section for details on chang- ing the v6 or v7 voltage. on the MAX8660, the com- bined power input for the reg6 and reg7 linear regulators is in67. on the max8661, in6 is the power input for reg6 (reg7 is not available on the max8661). reg6 and reg7 are disabled by default and must be enabled using the i 2 c serial interface. reg6 and reg7 have independent enable bits in the over2 register: en6 and en7 (table 9). to enable the regulators, set the corresponding enable bit. reg8 (vcc_bbatt) always-on regulator the output of reg8 (v8) is always active when the input voltage (v in ) is above the undervoltage-lockout threshold of 2.55v (max) and below the overvoltage- lockout threshold of 6.0v (min). the reg8 linear regula- tor is supplied from in and its output regulates to 3.3v and supplies up to 30ma. the internal reg8 pass ele- ment is 12 ? in dropout, providing a 180mv dropout voltage with a 15ma output current. connect v8 to vcc_bbatt for applications that use intel xscale processors. the rso output goes low if v8 is less than 2.2v (falling typ). ramp-rate control (ramp) reg1 and reg2 have a fixed soft-start ramp that elimi- nates input current spikes when they are enabled; 200? after being enabled, reg1 and reg2 linearly ramp from 0v to the set output voltage in 450?. when these regu- lators are disabled, the output voltage decays at a rate determined by the output capacitance, internal 650 ? discharge resistance, and the external load. the reg3 and reg4 output voltage have a variable lin- ear ramp rate that is set by a resistor connected from ramp to agnd (r ramp ). this resistor controls the out- put-voltage ramp rate during soft-start and a positive voltage change (i.e., 1.0v to 1.4v). the negative volt- age change (i.e., 1.4v to 1.0v) is controlled in forced- pwm mode, and when the ard bit is set in normal mode (table 9). figure 4 shows the relationship between r ramp and the output-voltage ramp rates. a 56k ? r ramp satisfies the typical requirements of intel xscale processors; 200s after being enabled, reg3 and reg4 linearly ramp from 0v to the set output volt- age at the rate set by r ramp . when reg3 and reg4 are disabled, the output voltage decays at a rate deter- mined by the output capacitance, internal 550 ? dis- charge resistance, and the external load. ramp rates vs. ramp-rate resistor r ramp (k ? ) ramp rate (mv/ s) 0 2 4 6 8 10 12 10 100 1000 reg3/4/5 dcrr reg3/4 ssrr to: 1v 1.4v 1.8v figure 4. soft-start and voltage-change ramp rates reg reg soft start ramp rate ssrr ssrr mv s vv rk reg reg reg dynamic change ramp rate dcrr dcrr mv sx rk out amp ramp 34 14 0 0014848 2 2 13 5 9 45 12500 822 1359 /(): . .(.( .)) // (): (. ( .) ) ? ? ? ? ? ? ? = [] ? [] ++ ? ? ? ? ? ? ? = ? [] ++
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications ______________________________________________________________________________________ 29 active ramp-down functionality is inherent in forced- pwm operation. in normal-mode operation, active ramp down is enabled by setting ard3 and ard4 (table 9). with ?ctive ramp-down?enabled, the regulator output voltage ramps down at the rate set by r ramp . with small loads, the regulator must sink current from the output capacitor to actively ramp down the output voltage. in normal mode, with ?ctive ramp-down?disabled, the regulator output voltage ramps down at the rate deter- mined by the output capacitance and the external load; small loads result in an output-voltage decay that is slow- er than that specified by r ramp , large loads (> c out x ramprate) result in an output-voltage decay that is no faster than that specified by r ramp . 80? after being enabled, reg5 linearly ramps from 0v to the set output voltage in 225?. the ramp rate during a positive voltage change (i.e., 1.8v to 1.9v) is set with r ramp . during a negative voltage change (i.e., 1.9v to 1.8v), the reg5 output voltage decays at a rate deter- mined by the output capacitance and the external load; however, ramp-down is no faster than the rate specified by r ramp . when reg5 is disabled, the output voltage decays at a rate determined by the output capacitance, internal 2k ? discharge resistance, and the external load. 60? after being enabled by i 2 c, reg6 and reg7 lin- early ramp from 0v to the set output voltage in 450?. reg6 and reg7 do not have positive voltage-change (i.e., 1.8v to 2.5v) ramp-rate control. during a positive voltage change, the output-voltage dv/dt is as fast as possible. to avoid this fast output dv/dt, disable reg6 or reg7 before changing the output. with this method, the soft-start ramp rate limits the output dv/dt, and therefore, the input current is controlled. during a nega- tive voltage change (i.e., 2.5v to 1.8v), the reg6 or reg7 output voltage decays at a rate determined by the output capacitance and the external load. when reg6 or reg7 is disabled, the output voltage decays at a rate determined by the output capacitance, internal 350 ? discharge resistance, and the external load. power sequencing enable signals (en_, pwr_en, sys_en, i 2 c) as shown in table 5, the MAX8660/max8661 feature numerous enable signals for flexibility in many applica- tions. in a typical application with the intel xscale processor, many of these enable signals are connected together. en1, en2, and en5 typically connect to intel? sys_en output. with this connection, reg5 is the first figure 5. v3/v4 enable logic en34 sda scl pv4 pv3 on reg4 pg4 lx4 en3 en4 batt v4 (vcc_sram ) on reg3 i 2 c pg3 lx3 batt v3 (vcc_apps ) maxim enable signal power domain hardware software intel enable signal v1 ( vcc_io ) (MAX8660/MAX8660a only) en1 v2 ( vcc_mem ) en2 v5 ( vcc_mvt ) en5 sys_en v3 ( vcc_apps ) en3 (over1) v4 ( vcc_sram ) en34 en4 (over1) pwr_en & pwr_i 2 c v6 ( vcc_card1 ) en6 (over2) v7 ( vcc_card2 ) (MAX8660/MAX8660a only) en7 (over2) standard i 2 c v8 ( vcc_bbatt ) always on
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications 30 ______________________________________________________________________________________ MAX8660 quiescent operating current (figure 3) power mode power domain state digital control state normal operating mode forced-pwm mode all on v1, v2, v3, v4, v5, v6, v7, and v8 are on en1/en2/en5 ( sys_en ) and en34 ( pwr_en ) are asserted. v6, v7 are enabled by i 2 c 250? 23ma v1, v2, v3, v4, v5, and v8 are on en1/en2/en5 ( sys_en ) and en34 ( pwr_en ) are asserted run, idle, and standby v6 and v7 are off v6 and v7 are disabled by i 2 c (default) 140? 22.9ma v1, v2, v5, and v8 are on en1/en2/en5 ( sys_en ) are asserted sleep v3, v4, v6, and v7 are off en34 ( pwr_en ) is deasserted; v6 and v7 are disabled by i 2 c (default) 90? 10ma deep sleep all supplies off except v8 en1/en2/en5 ( sys_en ) and en34 ( pwr_en ) are deasserted; v6, v7 are disabled by i 2 c 20? table 7. power modes and corresponding quiescent operating currents supply to rise (if in5 is connected to in). en34 typically connects to intel? pwr_en output. alternatively, reg3 and reg4 can be activated by the i 2 c interface (see the reg3/reg4 enable (en34, en3, en4) section for more information). reg6 and reg7 are activated by the serial interface. reg8 has no enable input and always remains on as long the MAX8660/max8661 are powered between the uvlo and ovlo range. all regu- lators are forced off during uvlo and ovlo. see the undervoltage and overvoltage lockout section for more information. note: the logic that controls the intel xscale proces- sor sys_en and pwr_en signals is powered from the vcc_bbatt power domain. reg3/reg4 enable (en34, en3, en4) reg3 and reg4 have independent i 2 c enable bits (en3, en4) and a shared hardware-enable input (en34). as shown in figure 5, the en34 hardware- enable input is logically ored with the i 2 c enable bits. table 6 is the truth table for the v3/v4 enable logic. note that to achieve a pure i 2 c enable/disable, connect en34 to ground. similarly, to achieve a pure hardware enable/disable, leave the i 2 c enable bits at their default value (en3 = en4 = 0 = off); v3 and v4 cannot be inde- pendently enabled/disabled using only hardware. note: a low mr drives rso low and returns the i 2 c registers to their default values: en3 = 0 and en4 = 0. power modes the MAX8660/max8661 provide numerous enable sig- nals (table 5) and support any combination for enabling and disabling their supplies with these signals. table 7 shows several power modes defined for intel xscale processors along with their corresponding MAX8660/ max8661 quiescent operating currents. table 6. truth table for v3 / v4 enable logic hardware input i 2 c bits en34 en3 en4 v3 v4 0 0 (default) 0 (default) off off 0 0 1 off on 0 1 0 on off x11onon 1xxonon x = don? care. note: forced-pwm currents are measured on the MAX8660 ev kit. currents vary with step-down inductor and output capacitor tolerance.
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications ______________________________________________________________________________________ 31 power-up and power-down timing figure 6 shows the power-up sequence for the intel xscale family of processors. in general, the supplies should power up in the following order: 1) power-up: v8 v5 v1 and v2 v3 and v4 2) reg6 and reg7 typically power external card slots and can be powered up and down based on appli- cation requirements. note that the intel xscale processor controls en1/en2/en5 with the same sys_en signal, yet intel? timing diagrams show that v5 is supposed to power up before v1 and v2. because of the intel xscale family? timing parameters, most systems connect en1/en2/ en5 together and drive them with sys_en . when pow- ering up, this connection ensures that v5 powers up before v1 and v2 (only when v5 is powered from in). intel xscale power configuration register (pcfr) the MAX8660/max8661 comply with the intel xscale power i 2 c register specifications. this allows the pmic to be used along with the intel xscale processor with little-to-no software development. as shown in table 9, there are many i 2 c registers, but since the intel xscale processor automatically updates the pmic through its power i 2 c interface, only the reg6 and reg7 enable bits need be programmed to fully utilize the pmic. v8 (vcc_bbatt) rso (nreset) t vbhrsth = 20ms, min (timed by pmic) t vbhbfh = 0s, min (timed by pmic) t bsthseh = 2.05s, max (timed by xscale) t sehvmh = sys_del time, max (timed by pmic) t vmhvsh1 = sys_del time, t sehvmh , max (timed by pmic) t vmhvsh2 = sys_del time - t, t sehvmh , max (timed by pmic) t sehph = sys_del time + 152 s, min t sehph = sys_del time + 153 s, max (timed by xscale) t bfhseh = 93.75 s, max (timed by xscale) lbo (nbatt_fault) en1/en2/en5 (sys_en) v5 (vcc_mvt) v1 (vcc_io) v2 (vcc_mem) en34 (pwr_en) scl from xscale (pwr_scl) sca from xscale (pwr_sda) nreset_out* from xscale v3 (vcc_apps) v4 (vcc_sram) t shroh = sys_del time +213 s, min t shroh = sys_del time +214 s, max (timed by xscale) t phlvth3 = pwr_del time (timed by pmic) t phlvth4 = pwr_del time (timed by pmic) *the MAX8660/max8661 do not directly use the intel xscale processor? nreset_out logic output. figure 6. power-up timing
MAX8660/max8661 the intel xscale processor contains a power manage- ment unit general configuration register (pcfr). the default values of this register are compliant with the MAX8660/max8661. however, wake-up performance can be optimized using this register: the pcfr register contains timers for the sys_del and pwr_del timing parameters as shown in figure 6. each timer defaults to 125ms. when using the MAX8660/max8661, these timers may be shortened to 2ms to speed up the overall system wake-up delay. enabling the ?horten wake-up delay?function (swdd bit) bypasses the sys_del and pwr_del timers and uses voltage detectors on the intel xscale processor to optimize the overall system wake-up delay. voltage monitors, reset, and undervoltage-lockout functions undervoltage and overvoltage lockout when the v in is below v uvlo (typically 2.35v), the MAX8660/max8661 enter its undervoltage- lockout mode (uvlo). uvlo forces the device to a dormant state. in uvlo, the input current is very low (1.5?) and all regulators are off. rso and lbo are forced low when the input voltage is between 1v (typ) and v uvlo . the i 2 c does not function in uvlo, and the i 2 c register contents are reset in uvlo. when the input voltage is above v ovlo (typically 6.35v) the MAX8660/max8661 enter overvoltage-lock- out mode (ovlo). ovlo mode protects the MAX8660/ max8661 from high-voltage stress. in ovlo, the input current is 25? and all regulators are off. rso is held low, the i 2 c does not function, and register contents are reset in ovlo. lbo continues to function in ovlo; however, since lbo is typically pulled up to v8 ( vcc_bbatt ), lbo appears to go low in ovlo because v8 is disabled. alternatively, lbo may be pulled up to in. reset output ( rso ) and mr input rso is an open-drain reset output. as shown in figure 1, rso typically connects to the nreset input of the intel xscale processor and is pulled up to v8 ( vcc_bbatt ). a low on nreset causes the processor to enter its reset state. rso is forced low when one or more of the following conditions occur: mr is low. v8 is below v rsoth (2.2v falling typ). ? in is below v uvlo (2.35v typ). ? in is above v ovlo (6.35v typ). rso is high impedance when all of the following condi- tions are satisfied: mr is high. v8 is above v rsoth (2.35v rising typ). ? uvlo < v in < v ovlo . the rso deassert delay (t vbhrsth = 24ms typ) has expired. when rso goes low, the MAX8660/max8661 i 2 c regis- ters are reset to their default values. if the mr feature is not required, connect mr high. if the rso feature is not required, connect rso low. low-battery detector ( lbo , lbf, lbr) lbo is an open-drain output that typically connects to the nbatt_fault input of the intel xscale processor to indi- cate that the battery has been removed or discharged (figure 1). lbo is typically pulled up to v8 ( vcc_bbatt ). lbr and lbf monitor the input voltage (usually a bat- tery) and trigger the lbo output (figure 7). the truth table in figure 7 shows that lbo is high impedance when the voltage from lbr to agnd (v lbr ) exceeds the low-battery rising threshold (v lbrth = 1.25v (typ). lbo is low when the voltage from lbf to agnd (v lbf ) falls below the low-battery falling threshold (v lbfth = 1.20v typ). on power-up, the lbr threshold must be exceeded before lbo deasserts. MAX8660 max8661 v lbfth 1.200v v lbrth 1.250v sq r lbr lbf in r3 r2 r1 agnd lbo + v8 (vcc_bbatt ) v lbf < v lbfth v lbr < v lbrth 0 lbf lbr truth table lbo v lbf < v lbfth v lbr > v lbrth 0 v lbf > v lbfth v lbr < v lbrth hold v lbf > v lbfth v lbr > v lbrth 1 figure 7. low-battery detector functional diagram high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications 32 ______________________________________________________________________________________
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications connecting lbf to lbr and to a two-resistor voltage- divider sets a 50mv hysteresis referred to lbf (hystere- sis at the battery voltage is scaled up by the resistor value), connecting lbf and lbr separately to a three- resistor voltage-divider (figure 7) allows the falling threshold and rising threshold to be set separately (achieving larger hysteresis). the figure 7 resistor val- ues are selected as a function of the desired falling (v lbof ) and rising (v lbor ) thresholds as follows: first, select r3 in the 100k ? to 1m ? range: where v lbor is the rising voltage at the top of r1 (typi- cally v in ) when lbo goes high, and v lbof is the falling voltage at the top of r1 when lbo goes low. for example, to set v lbor to 3.6v and v lbof to 3.2v, choose r3 to be 1m ? . then, r1 = 1.8m ? and r2 = 80k ? . if the low-battery-detector feature is not required, con- nect lbo to ground and connect lbf and lbr to in. internal off-discharge resistors each regulator on the MAX8660/max8661 has an inter- nal resistor that discharges the output capacitor when the regulator is off (table 8). the internal discharge resistors pull their respective output to ground when the regulator is off, ensuring that load circuitry always pow- ers down completely. the internal off-discharge resis- tors are active when a regulator is disabled, when the device is in ovlo, and when the device is in uvlo with v in greater than 1.0v. with v in less than 1.0v, the internal off-discharge resistors may not activate. thermal-overload protection thermal-overload protection limits total power dissipa- tion in the MAX8660/max8661. when internal thermal sensors detect a die temperature in excess of +160 c, the corresponding regulator(s) are shut down, allowing the ic to cool. the regulators turn on again after the junction cools by 15 c, resulting in a pulsed output dur- ing continuous thermal-overload conditions. a thermal overload on any of reg1 through reg5 only shuts down the overloaded regulator. an overload on reg6 or reg7 shuts down both regulators together. during thermal overload, reg8 is not turned off, and the i 2 c interface and voltage monitors remain active. i 2 c interface an i 2 c-compatible, 2-wire serial interface controls a variety of MAX8660/max8661 functions: the output voltages of v3?7 are set by the serial interface. each of the four step-down dc-dc converters (reg1/reg4) can be put into forced-pwm operation. reg3 and reg4 can be enabled by the serial inter- face or by a hardware-enable pin (en34). see the reg3/reg4 enable (en34, en3, en4) section for more information. reg6 and reg7 are activated only by the serial interface. the serial interface operates whenever v in is between v uvlo (typically 2.40v) and v ovlo (typically 6.35v). when v in is outside the i 2 c operation range, the i 2 c registers are reset to their default values. the serial interface consists of a bidirectional serial-data line (sda) and a serial-clock input (scl). the MAX8660/ max8661 are slave-only devices, relying upon a master to generate a clock signal. the master (typically the intel xscale processor) initiates data transfer on the bus and generates scl to permit data transfer. i 2 c is an open-drain bus. sda and scl require pullup resistors (500 ? or greater). optional resistors (24 ? ) in series with sda and scl protect the device inputs from high-voltage spikes on the bus lines. series resistors also minimize cross-talk and undershoot on bus signals. the intel xscale specification contains an extensive list of registers for various functions, not all of which are provid- ed on the MAX8660/max8661. the list in table 9 is a sub- set of the intel list as it relates to functions included in the pmic. even though the MAX8660/max8661 use a subset of the intel xscale-specified registers, they acknowledge writes to the entire register space (0x00 to 0xff). in intel xscale applications, the pullups are typically to vcc_iox. rrx v v x v v rrx vxv vxv lbor lbrth lbfth lbof lbfth lbor lbrth lbof 13 1 23 1 =? ? ? ? ? ? ? =? ? ? ? ? ? ? regulator internal off-discharge resistor value reg1 650 ? ?0% reg2 650 ? ?0% reg3 550 ? ?0% reg4 550 ? ?0% reg5 2k ? ?0% reg6 350 ? ?0% reg7 350 ? ?0% reg8 1.5k ? ?0% table 8. internal off-discharge resistor ______________________________________________________________________________________ 33
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications 34 ______________________________________________________________________________________ data bit register address register name r/w function 7654 3 2 1 0 rrrr r en4 (s_en) r en3 (a_en) 0x10 over1* w output-voltage enable register 1. enables/disables v3 and v4. see the reg3/reg4 enable (en34, en3, en4) section for more information. default 0 0 0 0 0 0 0 0 r en7** en6 0x12 over2 w output-voltage enable register 2. enables/disables v6 and v7. see the reg6/reg7 (vcc_card1, vcc_card2) section for more information. default 0 0 0 0 0 0 0 0 mvs mgo svs sgo rr avs ago 0x20 vcc1* w voltage-change control register. independently specifies that the v3, v4, and v5 output voltage must follow either target register 1 or 2. see table 10 . default 0 0 0 0 0 0 0 0 rrr v3 (vcc_apps) target 1 ?ee table 11 0x23 adtv1* w vcc_apps (v3) dvm target voltage 1 register. sets target 1 voltage for v3. default 0 0 0 1 1 0 1 1 rrr v3 (vcc_apps) target 2 ?ee table 11 0x24 adtv2* w vcc_apps (v3) dvm target voltage 2 register. sets target 2 voltage for v3. default 0 0 0 1 1 0 1 1 rrr v4 (vcc_sram) target 1 ?ee table 11 0x29 sdtv1* w vcc_sram (v4) dvm target voltage 1 register. sets target 1 voltage for v4. default 0 0 0 1 1 0 1 1 rrr v4 (vcc_sram) target 2 ?ee table 11 0x2a sdtv2* w vcc_sram (v4) dvm target voltage 2 register. sets target 2 voltage for v4. default 0 0 0 1 1 0 1 1 rrr v5 (vcc_mvt) target 1 ?ee table 12 0x32 mdtv1 w vcc_mvt (v5) target voltage 1 register. sets target 1 voltage for v5. default 0 0 0 0 0 1 0 0 rrr v5 (vcc_mvt) target 2 ?ee table 12 0x33 mdtv2 w vcc_mvt (v5) dvm target voltage 2 register. sets target 2 voltage for v5. default 0 0 0 0 0 1 0 0 v7 voltage ?ee table 13 v6 voltage ?ee table 13 0x39 l12vcr w ldo1 and ldo2 voltage-control register (v6 and v7 on MAX8660). specifies the v6 and v7 output voltage. v6 and v7 are enabled/disabled with over2. default 0 0 0 0 0 0 0 0 ard4 ard3 fpwm4 fpwm3 fpwm2 fpwm1** 0x80 fpwm w forced-pwm register. the fpwm_ bits allow v1, v2, v3, and v4 to independently operate in either skip mode or forced- pwm mode. see the reg1?eg4 step-down dc-dc converter operating modes section for more information. the ard_ bits allow the output voltage to be actively ramped down during negative voltage transitions see the ramp-rate control (ramp) section for more information. note that this is a maxim custom register that is not required by the intel xscale processor. default 0 0 0 0 0 0 0 0 table 9. i 2 c registers r means these data locations are designated reserved in the intel specification. note: the MAX8660/max8661 acknowledge attempts to write to the entire address space from 0x00 to 0xff, even though only a subset of t hose addresses actually exist in the ic. * these registers are accessed by the power i 2 c bus of the intel xscale processor. ** maintain these bits at their default 0 value for the max8661.
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications ______________________________________________________________________________________ 35 data transfer one data bit is transferred during each scl clock cycle. the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is high are control signals (see the start and stop conditions section for more information). each transmit sequence is framed by a start (s) condi- tion and a stop (p) condition. each data packet is 9 bits long; 8 bits of data followed by the acknowledge bit. the MAX8660/max8661 suport data transfer rates with scl frequencies up to 400khz. start and stop conditions when the serial interface is inactive, sda and scl idle high. a master device initiates communication by issuing a start condition. a start condition is a high-to-low transition on sda with scl high. a stop condition is a low-to-high transition on sda, while scl is high (figure 7). a start condition from the master signals the begin- ning of a transmission to the MAX8660/max8661. the master terminates transmission by issuing a not- acknowledge followed by a stop condition (see the acknowledge bit section for more information). the stop condition frees the bus. to issue a series of com- mands to the slave, the master may issue repeated start (sr) commands instead of a stop command in order to maintain control of the bus. in general, a repeated start command is functionally equivalent to a regular start command. when a stop condition or incorrect address is detect- ed, the MAX8660/max8661 internally disconnect scl from the serial interface until the next start condition, minimizing digital noise and feedthrough. register address register name bit name function 7mvs v5 ( vcc_mvt ) voltage select: 0?amp v5 to voltage selected by mdtv1 (default) 1?amp v5 to voltage selected by mdtv2 6 mgo start v5 ( vcc_mvt ) voltage change: 0?old v5 at current level (default) 1?amp v5 as selected by mvs 5 svs v4 ( vcc_sram ) voltage select: 0?amp v4 to voltage selected by sdtv1 (default) 1?amp v4 to voltage selected by sdtv2 4 sgo start v4 ( vcc_sram ) voltage change: 0?old v4 at current level (default) 1?amp v4 as selected by svs 3 r reserved 2 r reserved 1 avs v3 ( vcc_apps ) voltage select: 0?amp v3 to voltage selected by adtv1 (default) 1?amp v3 to voltage selected by adtv2 0x20 vcc1 0 ago start v3 ( vcc_apps ) voltage change: 0?old v3 at current level (default) 1?amp v3 as selected by avs table 10. dvm voltage-change register (vcc1, 0x20) sp sr scl sda t hd;sta t hd;sta t su;sto t su;sta figure 8. start and stop conditions
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications 36 ______________________________________________________________________________________ table 11. serial codes for v3 ( vcc_apps) and v4 ( vcc_sram ) output voltages register address register name data byte output voltage (v) 0x00 0.725 0x01 0.750 0x02 0.775 0x03 0.800 0x04 0.825 0x05 0.850 0x06 0.875 0x07 0.900 0x08 0.925 0x09 0.950 0x0a 0.975 0x0b 1.000 0x0c 1.025 0x0d 1.050 0x0e 1.075 0x0f 1.100 0x10 1.125 0x11 1.150 0x12 1.175 0x13 1.200 0x14 1.225 0x15 1.250 0x16 1.275 0x17 1.300 0x18 1.325 0x19 1.350 0x1a 1.375 0x1b 1.400 (default)* 0x1c 1.425 0x1d 1.450 0x1e 1.475 0x1f 1.500 0x20 1.525 0x21 1.550 0x22 1.575 0x23 1.600 0x24 1.625 0x25 1.650 0x26 1.675 0x27 1.700 0x28 1.725 0x29 1.750 0x2a 1.775 0x23 0x24 0x29 0x2a adtv1 adtv2 sdtv1 sdtv2 0x2b 1.800 *contact factory for other default voltages. table 12. serial codes for v5 output voltage table 13. serial codes for v6 and v7 output voltages register address register name data nibble output voltage (v) 0x0 1.8 (default) 0x1 1.9 0x2 2.0 0x3 2.1 0x4 2.2 0x5 2.3 0x6 2.4 0x7 2.5 0x8 2.6 0x9 2.7 0xa 2.8 0xb 2.9 0xc 3.0 0xd 3.1 0xe 3.2 0x39 l12vcr 0xf 3.3 register address register name data byte output voltage (v) 0x00 1.700 0x01 1.725 0x02 1.750 0x03 1.775 0x04 1.800 (default) 0x05 1.825 0x06 1.850 0x07 1.875 0x08 1.900 0x09 1.925 0x0a 1.950 0x0b 1.975 0x32 0x33 mdtv1 mdtv2 0x0c 2.000
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications ______________________________________________________________________________________ 37 acknowledge bit both the master and the MAX8660/max8661 (slave) generate acknowledge bits when receiving data. the acknowledge bit is the last bit of each 9-bit data packet. to generate an acknowledge (a), the receiving device must pull sda low before the rising edge of the acknowl- edge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (figure 9). to generate a not acknowledge ( a ), the receiving device allows sda to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves it high during the high period of the clock pulse. monitoring the acknowledge bits allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if a receiving device is busy or if a sys- tem fault has occurred. in the event of an unsuccessful data transfer, the bus master should reattempt commu- nication at a later time. slave address a bus master initiates communication with a slave device (MAX8660/max8661) by issuing a start condi- tion followed by the slave address. as shown in figure 10, the slave address byte consists of 7 address bits and a read/write bit (r/ w ). after receiving the proper address, the MAX8660/max8661 issue an acknowledge by pulling sda low during the ninth clock cycle. note that the r/ w bit is always zero since the MAX8660/ max8661 are write only. the intel xscale processor supports 0x68 (srad = gnd) as the i 2 c slave address. i 2 c write operation the MAX8660max8661 are write-only devices and rec- ognize the ?rite byte?protocol as defined in the smbus specification and shown in section a of figure 11. the ?rite byte?protocol allows the i 2 c master device to send 1 byte of data to the slave device. the ?rite byte?protocol requires a register pointer address for the subsequent write. the MAX8660/max8661 acknowledge any register pointer even though only a subset of those registers actually exists in the device. the ?rite byte?protocol is as follows: 1) the master sends a start command. 2) the master sends the 7-bit slave address followed by a write bit. 3) the addressed slave asserts an acknowledge by pulling sda low. 4) the master sends an 8-bit register pointer. 5) the slave acknowledges the register pointer. 6) the master sends a data byte. 7) the slave updates with the new data. t su:dat t hd:dat s scl sda 12 89 not acknowledge acknowledge figure 9. acknowledge bits s acknowledge scl sda 123 1 1 0 89 4567 0 1 0 srad 0 a srad 0 (gnd) 1 (in) slave address (write) binary hexadecimal 0x68 0x6a 0b 0110 1000 0b 0110 1010 r / w = 0 (write only) figure 10. slave address byte
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications 38 ______________________________________________________________________________________ 8) the slave acknowledges the data byte. 9) the master sends a stop condition. in addition to the write-byte protocol, the MAX8660/ max8661 recognize the multiple byte register-data pair protocol as shown in section b of figure 11. this proto- col allows the i 2 c master device to address the slave only once and then send data to multiple registers in a random order. registers may be written continuously until the master issues a stop condition. the multiple-byte register-data pair protocol is as follows: 1) the master sends a start command. 2) the master sends the 7-bit slave address followed by a write bit. 3) the addressed slave asserts an acknowledge by pulling sda low. 4) the master sends an 8-bit register pointer. 5) the slave acknowledges the register pointer. 6) the master sends a data byte. 7) the slave updates with the new data. 8) the slave acknowledges the data byte. 9) steps 5 to 7 are repeated as many times as the master requires. registers may be accessed in random order. 10)the master sends a stop condition. design procedure setting the output voltages the reg1 and reg2 regulators each have three preset voltages that are programmed with the set1 and set2 inputs. see the reg1 (vcc_io) step-down dc-dc converter and reg2 (vcc_io, vcc_mem) step-down dc-dc converters sections for more information. v8 is fixed at 3.3v and cannot be changed. v3?7 are set by the i 2 c interface. see the i 2 c interface section for more information. note that while operating in forced-pwm mode with an input voltage greater than 4.3v, the minimum output voltage of reg3 and reg4 is limited by the minimum duty cycle. in forced-pwm mode, the minimum output voltage for reg3 or reg4 is: 1 s number of bits r/w slave address 7 0 18 register pointer 1 18 data a 1 p 1 slave to master master to slave legend 1 s r/w slave address 7 0 18 register pointer x a 1 a a 18 data x a 1 p 1 8 register pointer n a 18 data n a 1 8 register pointer z a 18 data z a 1 a. writing to a single register with the ?rite byte?protocol b. writing to multiple registers with the ?ultiple-byte register-data pair?protocol number of bits number of bits number of bits a a figure 11. writing to the MAX8660/max8661
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications ______________________________________________________________________________________ 39 note that the above minimum voltage limitation does not apply to normal-mode operation. inductor selection calculate the inductor value (l ideal ) for each of reg1 through reg4 as follows: this sets the peak-to-peak inductor current ripple to 1/4 the maximum output current. the oscillator frequency, f osc , is 2mhz, and the duty cycle, d, is: given l ideal , the peak-to-peak inductor ripple current is 0.25 x i out(max) . the peak inductor current is 1.125 x i out(max) . make sure that the saturation current of the inductor exceeds the peak inductor current, and the rated maximum dc inductor current exceeds the maxi- mum output current (i out(max) ). inductance values smaller than l ideal can be used to reduce inductor size; however, if much smaller values are used, peak inductor current rises and a larger output capacitance may be required to suppress output ripple. larger inductance values than l ideal can be used to obtain higher output current, but typically require physically larger inductor size. refer to the MAX8660 ev kit data sheet for specific inductor recommendations. input capacitor selection the input capacitor in a step-down dc-dc converter reduces current peaks drawn from the battery or other input power source and reduces switching noise in the controller. the impedance of the input capacitor at the switching frequency should be less than that of the input source so that high-frequency switching currents do not pass through the input source. the input capacitor must meet the input-ripple-current requirement imposed by the step-down converter. ceramic capacitors are preferred due to their resilience to power-up surge currents. choose the input capacitor so that the temperature rise due to input ripple current does not exceed approximately 10?. for a step-down dc-dc converter, the maximum input ripple current is 1/2 of the output. this maximum input ripple current occurs when the step-down converter operates at 50% duty factor (v in = 2 x v out ). refer to the MAX8660 ev kit data sheet for specific input capacitor recommendations. output capacitor selection the step-down dc-dc converter output capacitor keeps output ripple small and ensures control-loop sta- bility. the output capacitor must also have low imped- ance at the switching frequency. ceramic, polymer, and tantalum capacitors are suitable, with ceramic exhibiting the lowest esr and lowest high-frequency impedance. output ripple due to capacitance (neglecting esr) is approximately: additional ripple due to capacitor esr is: v ripple(esr) = i l(peak) x esr refer to the MAX8660 ev kit data sheet for specific out- put capacitor recommendations. applications information power dissipation the MAX8660/max8661 have a thermal-shutdown fea- ture that protects the ic from damage when the die tem- perature exceeds +160 c (see the thermal-overload protection section for more information). to prevent ther- mal overload and allow the maximum load current on each regulator, it is important to ensure that the heat generated by the MAX8660/max8661 can be dissipated into the pc board. the exposed pad must be soldered to the pc board, with multiple vias under the exposed pad (ep) conducting heat to a ground plane. the junction-to-case thermal resistance ( jc ) of the MAX8660/max8661 is 2.7 c/w. when properly mount- ed on a multilayer pc board, the junction-to-ambient thermal resistance ( ja ) is typically 28 c/w. pc board layout and routing good printed circuit board (pc board) layout is neces- sary to achieve optimal performance. conductors car- rying discontinuous currents and any high-current path must be made as short and wide as possible. refer to the MAX8660 ev kit data sheet for an example of a good pc board layout. place the bypass capaci- tors for each power input pair (in to agnd, pv1 to pg1, pv2 to pg2, pv3, to pg3, and pv4 to pg4) as close as possible to the ic. the exposed pad (ep) is the main path for heat to exit the ic. connect ep to the ground plane with multiple vias to allow heat to dissipate from the device. v i xf xc ripple l peak osc out = () 2 d v v out in = l xv xdx d ixf ideal in out max osc = ? 41 () () vxv vxv min pv min pv 3 0 167 4 0 167 3 4 = = . .
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications 40 ______________________________________________________________________________________ ?ww?is a date code. ?aaa?is an assembly code. 8660e tlyww + aaaa 8660ae tlyww + aaaa 8661e tlyww + aaaa top view package marking + denotes lead-free packaging and marks pin 1 location. chip information process: bicmos
MAX8660/max8661 high-efficiency, low-i q , pmics with dynamic voltage management for mobile applications maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 41 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) qfn thin.eps

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